Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study
Pudi, Dhilleswararao; Harrison, Samuel Jigme; Stathis, Dimitrios; Boppu, Srinivas; Hemani, Ahmed; Cenkeramaddi, Linga Reddy
Peer reviewed, Journal article
Published version
Permanent lenke
https://hdl.handle.net/11250/3031245Utgivelsesdato
2022Metadata
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Originalversjon
Pudi, D., Harrison, S.J., Stathis, D., Boppu, S., Hemani, A. & Cenkeramaddi, L.R. (2022). Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study. Electronics, 11(18), 1-15. https://doi.org/10.3390/electronics11182965Sammendrag
State-of-the-art modern microprocessor and domain-specific accelerator designs are dominated by data-paths composed of regular structures, also known as bit-slices. Random logic placement and routing techniques may not result in an optimal layout for these data-path-dominated designs. As a result, implementation tools such as Cadence’s Innovus include a Structured Data-Path (SDP) feature that allows data-path placement to be completely customized by constraining the placement engine. A relative placement file is used to provide these constraints to the tool. However, the tool neither extracts nor automatically places the regular data-path structures. In other words, the relative placement file is not automatically generated. In this paper, we propose a semi-automated method for extracting bit-slices from the Innovus SDP flow. It has been demonstrated that the proposed method results in 17% less density or use for a pixel buffer design. At the same time, the other performance metrics are unchanged when compared to the traditional place and route flow.