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dc.contributor.authorBhanu, P. Veda
dc.contributor.authorRahul, Govindan
dc.contributor.authorKumar, Rajat
dc.contributor.authorSingh, Vishal
dc.contributor.authorJ, Soumya
dc.contributor.authorCenkeramaddi, Linga Reddy
dc.date.accessioned2022-04-21T11:13:36Z
dc.date.available2022-04-21T11:13:36Z
dc.date.created2021-06-04T15:45:14Z
dc.date.issued2021
dc.identifier.citationBhanu, P. V. Rahul, G. Kumar, R. Singh, V. Soumya, J. Cenkeramaddi, L. R. (2021). Fault-Tolerant Application-Specific Topology based NoC and its Prototype on an FPGA. IEEE Access, 9 76759-76779.en_US
dc.identifier.issn2169-3536
dc.identifier.urihttps://hdl.handle.net/11250/2991957
dc.description.abstractApplication-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant application-specific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a table-based fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) - 4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.en_US
dc.language.isoengen_US
dc.publisherIEEEen_US
dc.rightsNavngivelse 4.0 Internasjonal*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/deed.no*
dc.titleFault-Tolerant Application-Specific Topology based NoC and its Prototype on an FPGAen_US
dc.typePeer revieweden_US
dc.typeJournal articleen_US
dc.description.versionpublishedVersionen_US
dc.rights.holder2021 The Author(s)en_US
dc.subject.nsiVDP::Teknologi: 500en_US
dc.source.pagenumber76759-76779en_US
dc.source.volume9en_US
dc.source.journalIEEE Accessen_US
dc.identifier.doi10.1109/ACCESS.2021.3082852
dc.identifier.cristin1913825
dc.relation.projectScience and Engineering Research Board (SERB), Government of India, under Project ECR/2016/001389en_US
dc.relation.projectResearch Council of Norway Project 287918en_US
cristin.qualitycode1


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